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-- Project		: ECE 251 FINAL PROJECT
-- Author 		: Mahmut Yilmaz
-- Last Modified: 04/16/2007
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE work.all;

ENTITY delayed_counter_16 IS
	PORT(	clock	:	IN std_logic;
			clear	:	IN std_logic;
			count	:	IN std_logic;
			q		:	OUT std_logic_vector(15 DOWNTO 0)
	);
END delayed_counter_16;

ARCHITECTURE behav OF delayed_counter_16 IS
	SIGNAL pre_q : STD_LOGIC_VECTOR (15 DOWNTO 0);
BEGIN
    PROCESS (clock, count, clear)
    BEGIN
		IF clear = '1' THEN
	 	    pre_q <= x"FFFF";
		ELSIF (clock'event AND clock = '1') THEN
		    IF count = '1' THEN
				pre_q <= pre_q + 1;
		    END IF;
		END IF;
    END PROCESS;	
	
    q <= pre_q;

END behav;
